This invention, in general, relates to bit interleaving and bit deinterleaving techniques in wireless communication systems and, in particular, refers to a method of interleaving and deinterleaving using a single stage implementation in application specific integrated circuits (ASIC).
Error correcting codes are employed to minimize digital data errors in wireless communication systems. The error correcting codes are usually effective in correcting errors randomly distributed in the data. However, errors in digital transmission usually come in bunches or “bursts”, wherein a series of consecutive data bits are corrupted. Such channel burst errors frequently occur in wireless communication systems. The causes of these burst errors may be signal fading and channel impairment. Adopting an interleaving technique in conjunction with error correcting codes minimizes the effect of burst errors.
Bit-interleaving is a technique for rearranging the bit sequence of the transmitted data in a transmitter, prior to modulation. Upon receiving the data, a receiver restores the original bit sequence by a deinterleaving technique. The process of bit interleaving and deinterleaving effectively transforms the channel burst errors to random bit errors that may easily be corrected by error correcting codes.
Bit-interleaving is typically implemented in multiple stages to improve the interleaver robustness and performance. However, implementing a multistage bit interleaver is complex, as the multistage interleaving needs to be cascaded, wherein the output of one stage is provided as the input to the next stage.
In traditional interleaving methods, input bits are written into the memory sequentially one bit at a time and then read in the interleaved order. In multistage cascaded interleavers, the sequential mode of interleaving across various stages takes a large number of clock cycles to complete the interleaving operation.
Many interleaving methods use special memories that are written column by column and read row by row. These special memories include memory units organized into rows and columns, and are very complex to build in hardware.
Conventional interleavers and deinterleavers are usually specific to a particular type of interleaving and typically implement interleaving using complex hardware with special matrix memory blocks. The traditional methods implement the cascaded stages of interleaving separately. These methods employ different types of interleaving at each stage and results in increased hardware complexity. The traditional architectures may not be sufficiently scalable to meet high data rate demands.
Hence, there is an unmet need for a single stage bit interleaver that combines multiple stages of interleaving, is scalable to high data rates, has an efficient hardware implementation using standard memory blocks, and is capable of interleaving data using different interleaving techniques. The present invention relates to a bit-interleaver and deinterleaver architecture that addresses the above mentioned needs.